Toward a streamlined projection of small device bias temperature instability lifetime distributions

Effects of static and pulsed negative bias temperature stressing on lifetime in p-channel power VDMOSFETs

Threshold voltage shifts associated with negative gate bias temperature instability in p-channel power VDMOSFETs under the static and pulsed stress conditions are analysed in terms of the effects on device lifetime. The pulsed bias stressing is found to cause less significant threshold voltage shifts in comparison with those caused by the static stressing, which is ascribed to the effects of dy...

10th Int'l Symposium on Quality Electronic Design

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBT...

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Dynamic Voltage Scaling with Fault-Tolerance for Lifetime Operation

This work consists in a dynamic voltage scaling methodology, with Fault-Tolerance capability, to be used during circuits’ lifetime operation. Methodology implements on-line circuit monitoring, restricting power consumption by adjusting dynamically the power-supply voltage to the minimum value that prevent errors. Error free operation is achieved by using a cooperative work of global and local s...

Toward Engineering Modeling of Negative Bias Temperature Instability

CONTENTS 14.